PerlilogPerlilog is a command-line tool which generates Verilog modules from a set of files, which come in several other formats. It was originally designed to integrate Verilog IP cores. It's released as free software (GPL).
Motivation: Anyone who has needed to integrate a few Verilog modules into something working, knows it's a headache. It's not only a mechanic task, but also a source of bugs. Since Verilog modules' interface is basically wires, the integration task requires an accurate understanding of what each wire stands for, and how it's expected to behave. Having many details to keep track on, it's common that undesidered
Perlilog's main concept is that handling IP cores (and Verilog modules in general) should be intuitive. We think about IP cores as black boxes, so we should also relate to them as black boxes when connecting them. When connecting cores, we imagine that as drawing a thick line between them. So should the connection be done, when actually integrating the system.
Perlilog introduces an alternative concepts for connecting between cores. The main issues are:
Perlilog is also useful for much simpler tasks, such as massive connection of Verilog module's inputs and outputs to pads, and other tasks that are readily performed with Perl scripts. It's a good starting point for writing a Perl script which handles Verilog code, even for the simpler tasks (and hence the project's name, as a "mixture" between Perl and Verilog).
The idea for the project arose when working for a project with Flextronics Semiconductors in Israel. They also supported the project warmly.
The project's home page is http://www.opencores.org/perlilog/.
Last modified on Thu May 17 17:30:00 2012. E-mail: