Curriculum Vitae


Name Eli Billauer
Education B.Sc. in Electrical Engineering at the Technion (Israel), summa cum laude
Residence Haifa, Israel


Carrying out freelance projects for companies residing all over Israel, possibly abroad. Short-term assignments are welcomed, but working relationships usually turn out lasting for long periods.


  • Verilog -- Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs. Also with experience in writing Verilog for ASIC. High awareness of device targetting in source code. Careful and secure clock domain crossings.
  • Linux -- Kernel programming capabilities (drivers and core code), as well as in-depth knowledge of user space applications. Experienced with Linux as a system maintainer, user space programmer and kernel space programmer for fullblown computers as well as embedded systems (e.g. ARM Cortex A9 core and Xilinx' Microblaze soft processor).
  • MATLAB -- Clean and fast functions, following standard conventions. Wide experience in large simulations and proper display of the results. Good knowledge of the syntax and special functions.
  • C -- Writing for UNIX (gcc) as well as DSP implementations and PIC processors. Clean and portable code is supplied. Optimization for fast performance by reading assembly code.
  • Perl -- Deep familiarity with the language, both for scripting and application development. Has developed large projects in Perl (see Perlilog and Eobj).
  • Some experience with Pascal (including Delphi 4), and assembly language (TI 54x and 6502). Some HTML, Java and JavaScript for web purposes. Nontrivial MySQL database managements and SQL query formation. Small hacks in LISP, mainly for Emacs. Catches up new languages quite easily.
Embedded / ARM:
  • Properly written device drivers for embedded Linux, taking attributes from the Flattened Device Tree (FDT) / Open Firmware (OF) framework.
  • Setting up cross compilers and boot images from scratch (using Buildroot, with custom kernel and Busybox configuration).
  • Cross compilation of the Linux kernel and user space application for ARM.
  • Adaption of fullblown desktop distributions (e.g. Linaro / Ubuntu) for ARM.
  • Design and implementation of IP cores for Microblaze / Zynq EPP (ARM) as AXI3/AXI4 (AMBA) bus peripherals, proper mapping in the Device Tree and integration with Linux as a standard device.
  Authorized trainer of Xilinx' official courses. Delivers the following courses for Logtel, which is the Authorized Training Provider for Xilinx courses in Israel:
  • Fundamentals of FPGA Design
  • Designing for Performance
  • Advanced FPGA Implementation
  • Designing with the Virtex-4 Family
  • DSP Implementation Techniques for Xilinx FPGAs
Signal Processing:
  • Design of signal processing elements, simulation in MATLAB, efficient implementation on DSP or FPGA/ASIC.
  • Design of modems (including unconventional communication channels), simulation in MATLAB, and implementing on DSP. Familiarity with scramblers and FEC. Knowledge in RF to the extent needed to test a complete transmission chain.
  • Familiar with common Internet protocols, especially low-level (TCP, UDP, IP).
  • Knowledge of the PCI Express protocol to the extent of designing a peripheral on FPGA (at TLP level), and write the Linux kernel module driver for it.
  • Experience with Gigabit Transceivers (GTX, MGT) on FPGA, SFP+ based fiber optics, and use of these for PCI Express
Human interaction:
  • Experienced in teaching, both frontal and one-on-one. Several projects have included a phase of passing knowledge to company's in-house engineers.
  • Works well in teams, as member or leader. Physical distance is seldom an obstacle.
  • High ability to join existing teams and organizations. Readily adapts to company's way of thinking.


2000- Freelancer (see below)
1993-1999 Military service, carried out as an Electrical Engineer. Took part in mainly two large projects. Was the team leader of one of these projects, which involved 4 dedicated engineers and about 10 others for periods above 2 months.


  (in reverse order; last project taken listed first)
  1. For the XillyUSB project:
    • Design and FPGA implementation of a full USB 3.0 SuperSpeed device stack, based upon the FPGA's gigabit transceiver: The physical layer, link layer and protocol layers were implemented from scratch.
    • An application protocol layer was implemented on the FPGA.
    • Writing device drivers for Windows and Linux (the latter is part of the official Linux kernel).
    • Mechanical plastic enclosure and PCB design of a physical adapter module that allows connecting a Micro-B SuperSpeed USB 3.0 cable to an FPGA board having an SFP+ cage (sfp2usb).
  2. Design and implementation of a medical signal capture system (FPGA part) + setting up an SFP+ based optical PCI Express link for electrical insulation, based upon Avago (formerly PLX) PEX86xx PCIe switch. The work involved the detailed wiring and register setup of the PCIe switch.
  3. Design and implementation of a video processing system with 10 DVI receivers and 10 DVI transmitters, and two 4k DisplayPort outputs for real-time composing of output images from scaled sub-images of the video inputs. A DDR3 SODIMM memory was used for image data storage and retrieval.

    10 bidirectional inter-FPGA Gigabit Transceivers (GTX) links for 10 Gbit/s each were set up to carry the image data to front-end FPGAs which were connected to the DVI chips, in order to cope with the vast pin count. A custom transport protocol and a standard scrambler were implemented on the link.

  4. Setting up a full graphical Linux desktop distribution for the Zedboard (Xilinx Zynq-7000 EPP), based upon Ubuntu for ARM, including
    • Setting up the boot image and cross compiler from scratch using Buildroot
    • Desiging a VGA adapter module in Verilog for the logic fabric, attaching it to the processor on the AXI3 bus, mapping the device on the Device Tree, and writing the Linux device driver making it act like a standard frame buffer device. As a result, the on-board VGA connector became the system's console for plain text and X-Windows automatically.
    • Adaption of the distribution: Adding on-board sound support, linux kernel headers to allow native module compilation, applet for displaying CPU usage on the on-board OLED display etc.
  5. Design and implementation of a generic PCI Express-based framework for communication between a host computer and a Xilinx FPGA (Xillybus). The project involved, among others:
    • FPGA logic taking an arbitrary number of data streams with standard FIFO interface, and connecting these efficiently and seamlessly with a Xilinx Endpoint Block Plus PCIe IP core, sending and receiving Transaction Layer Packets (TLPs).
    • BAR-addressed registers, a DMA engine, message passing mechanism, and a round-robin arbiter in both directions for the data streams.
    • A generic, autodetecting driver for Linux and Microsoft Windows (the latter following the Windows Driver Model, WDM).
    • Implementation of Perl scripts for automatic generation of Verilog sources, setting up a custom IP core for synthesis according to configuration parameters.
  6. Implementation in Verilog of an SPI bus master with the capability of reading from, erasing and writing to a serial flash memory, using a well-established protocol.
  7. Theoretic design and implementation of spatially varying white balance, for compensation of time-constant color tints in the image. The project included a utility (written in C) for setting the white balance parameters. The smoothly varying color balancing of the Bayer-sampled image was implemented in Verilog for a small Xilinx FPGA.
  8. Fully synchronous implementation of an I2C/SMBus slave in Verilog (for FPGA) giving access to registers, including burst reads and writes, following a commonly used protocol.
  9. Research and development of a controller for a MEMS device: Creating custom laboratory equipment and utilizing it to attain desired mechanical control of the device. Handling all aspects of the custom equipment except for the board design: The signal flows, FPGA design and implementation, communication with a PC computer for data acquisition and control, and finally, the mechanical control loop.

    The project included several experiments with the MEMS device, with the aim to learn its dynamic behavior; Different waveforms were applied, data was captured and analyzed with MATLAB, this process concluded with a suggested mechanism for controlling the physical motion of the device.

    The following distinctive functional blocks were designed and implemented on the FPGA:

    • A linear-interpolated high-resolution NCO for generation of a clean low-frequency sine wave to drive the mechanical device with.
    • A register interface for configuration, running over a USB channel, based upon the Cypress CY7C68013A chip.
    • A buffer acquisition mechanism for transporting samples of selected signals to the PC through the USB channel.
    • A PI-type linear phase-locked loop for keeping the mechanical device in resonance vibration. The phase sensor was based on sensing swings in capacitance, by applying an RC oscillator and measuring the oscillation frequency.
    A Windows GUI application for the PC computer (under Microsoft Windows) was also written in order to allow convenient tuning of the equipment's parameters through the USB connection.
  10. Stabilization, maintenance and adding features to Xilinx FPGA Verilog code previously developed by client, for two separate in-production medical systems (endoscopy) as follows:
    • Clock improvements: Reimplementing gated clocks with Xilinx clock resources (CLKDLL/DCM) and flip-flop enables, assuring glitch-free clocks to logic fabric.
    • Proper handling of global asynchronous reset to assure that system power ups to a known state.
    • Revision of UCF timing constraints to avoid timing violations in connections with other devices, as specified in those devices' datasheets, following strategies recommended by Xilinx. Also, applying multi-cycle paths and false paths where applicable.
    • Improvement of clock domain crossings and sampling of external source-clocked signals for reliable operation.
    • Increasing repeatability and I/O timing performance by utilizing IOB registers in the vast majority of I/O interfaces.
    • Ensuring the system's complatibility with VGA computer display monitors (HD15 and DVI) by enforcing VESA standard as specified in VESA's Computer Display Monitor Timing (DMT) specification: Adjusting the timing of the existing video timing generator for proper sync timings, back and front porches and blanking.
    • Adding support of HDTV analog YPbPr outputs 720p and 1080i as specified in SMPTE 296M and SMPTE 274M, using a dedicated chip on one system, and using only D/A converters on the other (and hence implementing the standard waveform completely along with the trilevel sync and broad pulse). Also enforcing SMPTE 253M on RGsB outputs (also known as Sync on Green or SOG).
    • Implementation of real-time rotation, zoom and diplacement with arbitrary rotation angle, zoom factor and center position. The processing engine performs a two-dimensional 2x2 pixel linear interpolation for each output pixel produced, allowing a smooth camera-like travelling on the source image.
    • Implementation of a real-time unsharp mask filter.
  11. Architecture design and implementation of a complete real-time image processing system for detecting time-spatial transient events, according to the client's core-knowledge custom algorithm. The system was implemented in Verilog on a Xilinx Virtex-4 device, for handling up to 100 MPixel/s. This project included, among others, the following tasks:
    • Implementing the custom signal processing algorithm in a reference fixed-point C application, along with improvement suggestions for accurate performance. After client's internal testing of the reference code, Verilog code was written and verified on the FPGA to match the reference code to the bit.
    • Utilizing a MiG-1.4 based DDR2 memory controller, running at 266 MHz (Jedec DDR2-533) against a Micron SDRAM (fixing and reporting some bugs on the way)
    • Implementation of a Camera Link interface (ent-to-end from LVDS inputs to pixel FIFO) compliant to Automated Imaging Association's Cameralink spec version 1.1. For reliable data capture, the optimal LVDS input sampling phase is searched for prior to operation, taking advantage of the Virtex' phase shifting capabilities.
    • Implementation of an efficient high-speed (480 Mbits/sec) USB bidirectional bulk link between a Windows-based PC and the FPGA, allowing simple end-to-end stream interfaces from the PC to internal FIFOs in the FPGA. The work included Verilog code for the Xilinx device which implements the controller and interface with the Cypress CY7C68013A chip, the 8051-like firmware running on the Cypress chip, and template applications running under Windows, using Cypress' own drivers.

      In addition, a simple packet protocol (with checksums and channels) was implemented over a bulk endpoint pair, with their PC software drivers written as well.

  12. Programming of an Atmel AT94K FPSLIC device, both FPGA part (Verilog) and AVR processor (C language), communicating between them via the common SRAM interface.
  13. Implementation of an on-the-fly (MCU-wise) baseline JPEG encoder as a Verilog IP core. The core consists of 2D-DCT, quantization, zigzag scanning, run-length encoding, and entropy coding. The output data is bitwise compatible with jpeglib when used with the same tables and parameters. Restart markers are supported. Runs at 90 Msamples/sec on Xilinx Spartan-3, one sample per clock cycle.
  14. Implementation of a driver for HP color printer, generating PCL3 stream from a color pixel map on the fly. The driver included color space conversion to CMYK, dithering with the Floyd-Steinberg algorithm and PCL3 encoding. The driver was implemented in C for ARC core processor with a restricted amount of RAM.
  15. Design of memory manager for NAND flash for purpose of logging data. Very high reliability was requested despite the utilization of flash memories with a non-negligible probability of bit failure.
  16. Writing C code which parses elements of X.509 certificates, according to their ASN.1 definition in RFC 3280.
  17. Translation of several crypto algorithms (DES/3DES, RSA and RC4) to pseudo-code, which was easily coded in Verilog by a fellow engineer. Creation of test environment and test sequences using openSSL.
  18. C programming and work with ICE on a 8051.
  19. Implementation of some basic signal processing functions on a PIC 16F877 processor.
  20. MATLAB simulation of a QAM demodulator for xDSL applications. Examining the complexity of the equalizers necessary to overcome certain conditions of the copper wire deployment.
  21. Implementation of Verilog modules with signal processing orientation: Quadrature counters, pattern generators etc.
  22. Design of a Sigma-Delta modulator for audio signals for CD quality. Simulations in MATLAB and implementation as a reusable Verilog IP core (synthesizable code and test bench).
  23. Development of signal processing algorithms for extracting information from optical sensor signals. Verification of the algorithms with MATLAB against real-life samples. Real-time implementation on TI's 5402 DSP.
  24. Consulting and assistance to a cable-modem startup company during their first stages.
  25. Implementation of a GSM packet transmitter, including modulator and bit manipulation as required to generate a legal traffic packet. The project involved simulation in MATLAB, implementation on TI's 5402 DSP, RF setup for testing and verification of compliance with GSM standards.
Last modified on Thu Aug 3 17:24:24 2023. E-mail: